`include "ascon_define.v"

module `TX_BUF_2_32B_64
    (
    input                                        clk_i,
    input                                        rstn_i,

    input                                        en_i,
    input                                        wen_i,
    input                     [`BUF_ADDR_W-1 :0] waddr_i,
    input                            [`M_W-1 :0] wdata_i,

    input                  [`AHB_BUS_ADDR_W-1:0] raddr_i,
    output reg             [`AHB_BUS_DATA_W-1:0] rdata_o
    );

wire                                             en_0 , en_1;
wire                                             wen_0  , wen_1;
wire                       [`AHB_BUS_DATA_W-1:0] rdata_0, rdata_1;
wire                       [`AHB_BUS_DATA_W-1:0] wdata_0, wdata_1;

wire                           [`BUF_ADDR_W-1:0] waddr;

wire                                       [0:0] rByte_sel;
wire                           [`BUF_ADDR_W-1:0] raddr;

assign waddr                                     = waddr_i;

assign raddr                                     = raddr_i[3+`BUF_ADDR_W-1:3];
assign rByte_sel                                 = raddr_i[2:2];

assign en_0                                      = en_i;
assign en_1                                      = en_i;

assign wen_0                                     = wen_i;
assign wen_1                                     = wen_i;

assign wdata_0                                   = wdata_i[`AHB_BUS_DATA_W-1:0];
assign wdata_1                                   = wdata_i[`M_W-1:`AHB_BUS_DATA_W];

always@(*)begin
    case (rByte_sel)
        1'b0 : rdata_o       = rdata_0; // msb->lsb(left->right)
        1'b1 : rdata_o       = rdata_1;
        default : rdata_o    = `AHB_BUS_DATA_W'b0;
    endcase
end

// 第一字节
`RAM_32B_64
u_ram_0
    (
    .clk_i                             (clk_i                                  ),
    .rstn_i                            (rstn_i                                 ),

    .en_i                              (en_0                                   ),
    .wen_i                             (wen_0                                  ),
    .waddr_i                           (waddr                                  ),
    .wdata_i                           (wdata_0                                ),

    .raddr_i                           (raddr                                  ),
    .rdata_o                           (rdata_0                                )
    );

// 第二字节
`RAM_32B_64
u_ram_1
    (
    .clk_i                             (clk_i                                  ),
    .rstn_i                            (rstn_i                                 ),

    .en_i                              (en_1                                   ),
    .wen_i                             (wen_1                                  ),
    .waddr_i                           (waddr                                  ),
    .wdata_i                           (wdata_1                                ),

    .raddr_i                           (raddr                                  ),
    .rdata_o                           (rdata_1                                )
    );
endmodule